Integrated circuit (“IC”) die or “die” are typically mounted in or on a package in order to form a semiconductor device, also referred to as a “semiconductor device package”, a “semiconductor chip package”, a “semiconductor package” or an “IC device package”. Mounting of an IC die to a package facilitates subsequent attachment of the resulting semiconductor device to a printed circuit board (“PCB”) or other component of an electronic assembly. There are three typical processes available for semiconductor device assembly. Generally, these processes are referred to as the eutectic process, the epoxy process, and the solder process. Regardless of which process is used, the process results in mechanical and electrical connections between a semiconductor die and a corresponding lead frame of the semiconductor package.
FIG. 5 is a side view of a typical generic semiconductor device package 5 under the prior art. The semiconductor package 5 includes a bottom plate portion 6, referred to as “pads” on the lead frame, and terminals 2a and 2b. A semiconductor die 1 is placed on the bottom plate portion 6, and secured to the bottom plate portion 6, typically using a solder material or Gold-Silicon intermetallic bond produced when die bonding with high temperature (approximately 375 degrees Celsius). The semiconductor die 1 has a metalized region 7a and 7b (typically aluminum) that defines a connection area for a top surface of the semiconductor die 1. The metalized region 7a and 7b of the die is electrically connected to terminals 2a and 2b using one or more gold/copper wires 4. The wire 4 is ultrasonically bonded first to the metalized region 7a and then bonded 8a and 8b to the terminal 2a. 
The eutectic semiconductor assembly process generally begins with a silicon wafer having gold plating on one side, and continues with the following steps in the following order: dicing; die bonding; wire bonding; molding; strip marking; plating trimming and forming; and testing and taping. The eutectic process requires that the step of plating gold on one side of the wafer be performed in the wafer fabricating house (unless the assembly site has this process capability as well as wafer thinning capability and wafer probe test capability). This gold plating step is an extra step in the assembly process when compared to other typical semiconductor assembly processes.
The die bonding of the eutectic process is required to be performed at a high temperature of approximately 375 degrees Celsius so as to form an adequate bond between the gold plating the bottom plate portion 6. A problem can arise when performing the die bonding that relates to the strength of the bond between the gold plating and the silicon material of the die. Die shear testing has shown the absence of silicon or poor silicon residue on the lead frame bonded pad after shearing the die 1 from the bottom plate portion 6, indicating a poor bond between the gold plating and the silicon. FIG. 6A shows a lead frame bonded pad 6 of a semiconductor package with no/poor silicon residue 9a remaining after pushing away the semiconductor die 1 (i.e., shear test), under the prior art. By comparison, FIG. 6B shows a lead frame bonded pad 6 of a semiconductor package with normal silicon residue 9b remaining after pushing away the semiconductor die 1, under the prior art.
The epoxy/solder semiconductor assembly processes generally begin with a silicon wafer processed as follows: dicing; die bonding to include dispensing epoxy/solder; curing; wire bonding; molding; strip marking plating; trimming and forming; and testing and taping. While the epoxy and solder processes are suitable for big die, it is difficult to solder bond die smaller than approximately 0.3 mm (millimeters) by 0.3 mm. For small die, overflow and rotation are the major problems when dispensing epoxy or solder. FIG. 7A shows the overflow of excess epoxy/solder 3 around a small semiconductor die 1, under the prior art. The semiconductor die 1 is electrically connected to a terminal using a wire 4 bonded 8 to the terminal. There is so much excess epoxy/solder 3 on the semiconductor die 1 that the epoxy/solder surface consumes more than half of the die height surface and leaves a large amount of epoxy/solder 3 in place around the semiconductor die 1. FIG. 7B shows a normal amount of epoxy/solder 3 around a small semiconductor die 1, under the prior art. Further, epoxy/solder 3 sometimes does not dispense smoothly resulting in uneven and/or inconsistently dispensed dots on the lead frame pads; this can cause immediate or long-term electrical failure of the semiconductor device. Additionally, both epoxy and solder processes require the use of a dispensing head for the die bonding machine.
In the drawings, the same reference numbers identify identical or substantially similar elements or acts.